1. Field of the Invention
This invention relates to improvements in large and very large scale integrated (LSI and VLSI) circuits, and more particularly to improvements in methods and apparatuses for testing such circuits.
2. Description of the Prior Art
With advancing developments of very large scale integrated (VLSI) semiconductor circuits, the number of circuit elements, such as gates, flip-flops, and memory cells, on an integrated chip is expanding to very large numbers. This expansion has given rise to increasing problems in testing the chips, both in their original manufacturing test and during their use in the field. Some of the problems encountered in VLSI testing are as follows.
The complexity and cost of test generation and fault simulation increases with an increasing number of circuit elements. It has been reported, in fact, that the test generation and fault simulation cost for a chip grows approximately proportionally to the third power of the number of gates and flip-flops on the chip. This problem has been recognized, for example in "Testing logic networks and designing for testability", by T. W. Williams et al., Computer, Vol. 12, No. 10, October 1979, pp. 1-21.
Similarly, the length and execution time of tests increase with the increasing complexity of chips. Since the chip manufacturing cost is expected to decrease over time as production volume increases, the testing cost is expected to become a significant portion of the overall chip cost.
Fault coverage provided by existing test methods is not adequate since most of the tests used presently are designed to detect only the so-called single "stuck-at" faults. Very small circuit features, low voltage levels, and very large number of devices present on a VLSI chip are expected to give rise to many failure modes which cannot be modeled or detected as single "stuck-at" faults.
Presently, conventional testers analyze the serial bit streams produces at a particular point within the circuit under test. A probe is provided to physically contact a test pad or pin, and the logic signals at the point are examined. As the size of VLSI circuits is reduced further and further, it is becoming increasingly difficult to access many internal points on a VLSI chip using a conventional tester via a limited number of input/output pads or pins.
Conventional test methods when applied to VLSI circuits are also faced with enormous test data volume. For example, in a VLSI processor housed in a 64 pin package, if each machine instruction requires an average of 5 machine cycles, the test data volume for 10,000 machine instructions in a test program translates into over 3 million bits.
In the past, various testing techniques have been developed. For example, IBM has developed a technique referred to as "level sensitive scan design", in which a complex sequential circuit is transformed during a test mode into simple combinational logic and one (or more) serial shift, or scan, registers. A desired test pattern is serially shifted into this scan register from an external pin (i.e. from an external test pattern source), and once the test pattern is stored in the scan register, it is applied to the combinational logic under test. The test result produced by the combinational logic alters the contents of the scan register. The test result stored in the scan register can be serially shifted out to an external pin, for comparison with an expected test result outside the chip. It can therefore be seen that the scan register provides a convenient and easy means to apply test patterns, and to read out the test results produced by the combinational logic, which may be "buried" deep inside the chip. One of the disadvantages of this type of testing approach is that it is operated at a relatively slow speed since the test patterns and results are shifted into and out of the scan register in a bit-serial fashion. Thus, the testing is not accomplished at full operational speed, and errors which result, for example, because of timing inaccuracies or flaws may not be disclosed by the test.
Another well known test technique is called "serial signature analysis", and is incorporated in an instrument manufactured by Hewlett Packard Company. Serial signature analysis is a data compression technique used to compress test result data produced in the form of a serial bit stream. It is based on the principle of cyclic redundancy check, which is implemented by means of a linear feedback shift register. For example, in a 16 bit serial signature analyzer, the outputs of the 7th, 9th, 12th, and 16th flip-flops in the linear feedback shift register are fed back to the 1st flip-flop through an exclusive-or gate. The input of the 1st flip-flop is an exclusive-or combination of the feedback signal, and the serial data input. The exclusive-or gates perform a modulo 2 sum operation, a linear operation, on its inputs. Therefore the feedback register of this type is referred to as a linear feedback shift register, and essentially performs a polynomial division on the serial input data stream.
In products embodying this technique, the serial bit stream of test result is compressed by a serial signature analyzer and presented in the form of four hexadecimal digits known as the signature of the node producing that particular serial bit stream test result. The signature produced by a node is usually visually compared with the expected signature.
Reference is made to B. Konemann et al., "Built-in Logic Block Observation Techniques", Digest of papers, 1979 Test Conference, 79CH1509-9C, October 1979, pp. 37-41 which discloses the extension of serial signature analysis techniques to the compression of a parallel bit stream. The circuit ordinarily used is similar to that used for compressing serial bit streams, but the input of each flip-flop comes from an exclusive-or combination of the output of the previous flip-flop with each member of the parallel bit stream providing an input to each respective flip-flop. This type of signature analysis is referred to as parallel signature analysis, and results in considerable savings in time from that required by serial signature analysis techniques.
Other papers in this area to which reference is made are as follows. "Signature Analysis", Hewlett-Packard Journal, Vol. 28, No. 9, May, 1977; "Shift-register sequences", by S. W. Golomb, Holden-Day, Inc., San Francisco, 1967; and "Signature analysis: A new digital field service method" by R. A. Frohwerk, Hewlett Packard Journal, Vol. 28, No. 9, May, 1977.